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Additional resources for 8-bit AVR Microcontroller with 1К Byte Flash ATtiny15L
Timer/Counter1 is implemented as an up-counter with read and write access. Due to synchronization of the CPU and Timer/Counter1, data written into Timer/Counter1 is delayed by one CPU clock cycle. 30 ATtiny15L 1187F–AVR–06/05 ATtiny15L Timer/Counter1 Output Compare RegisterA – OCR1A Bit 7 6 5 4 3 2 1 0 $2E MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 OCR1A The Output Compare Register 1A is an 8-bit read/write register. The Timer/Counter Output Compare Register 1A contains the data to be continuously compared with Timer/Counter1.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX affects the way the result is read from the registers. If ADLAR is set, the result is left-adjusted. If ADLAR is cleared (default), the result is right-adjusted. 0: ADC Conversion Result These bits represent the result from the conversion. For the differential channel, this is the value after gain adjustment, as indicated in Table 20 on page 47.
A compare match will set (one) the Compare Interrupt Flag in the CPU clock cycle following the compare event. Timer/Counter1 in PWM Mode When the PWM mode is selected, Timer/Counter1 and the Output Compare Register A (OCR1A) form an 8-bit, free-running and glitch-free PWM with outputs on the PB1(OC1A) pin. Timer/Counter1 acts as an up-counter, counting up from $00 up to the value specified in the second Output Compare Register OCR1B, and starting from $00 up again. When the counter value matches the contents of the Output Compare Register OCR1A, the PB1(OC1A) pin is set or cleared according to the settings of the COM1A1/COM1A0 bits in the Timer/Counter1 Control Registers TCCR1.